(a) Field of the Invention
The present invention relates to a mask for alignment, such as a reticle mask for use in a reduction projection aligner and a contact aligner mask, used for a photolithographic technique during the manufacture of a semiconductor integrated circuit, and a method for inspecting such a mask.
(b) Description of the Related Art
A mask in general, and specifically a reticle mask by way of example, comprises a glass substrate having a peripheral region in which a reticle alignment mark is provided and a central region in which a circuit pattern area is surrounded by a stripe light shielding area. Since the alignment mark, the light shielding area and the circuit pattern are defined by an electron-beam lithographic system, it is considered that a high accuracy is achieved in the relative locations among the alignment mark, light shielding area and the circuit pattern. If this is true, it allows an exact transfer of the circuit pattern of the reticle mask onto a semiconductor wafer, by using an exposure technique after indexing of the alignment mark of the reticle mask with respect to a position mark in a pattern formed on the semiconductor wafer during a preceding step.
FIG. 1 shows a reticle mask described in JP-A-4(1992)-102851, which proposes relative position measuring marks 34 on four corners of a glass substrate 36 in order to enable an inspection of positional relationship on the semiconductor wafer among a group of patterns including alignment marks 33, a stripe light shielding area 32 and a circuit pattern area 38 surrounded by the stripe light shielding area 32. It is assumed therein that a high accuracy is established in the relative positional relationship between the reticle alignment marks 33 in the peripheral region and the circuit patterns 31 located in the central region surrounded by the light shielding area, allowing an assumption that substantially no positional offset exits between these patterns.
However, if a drift in the electron beam occurs in the electron-beam lithographic system used to fabricate a mask in the course of drawing a pattern by the electron beam, there occurs an offset between the circuit pattern and the reticle alignment marks in the peripheral region. That is, an exact positioning or indexing is not always achieved with respect to a pattern formed on the semiconductor wafer by utilizing the reticle alignment marks, wherein an offset sometimes occurs between the circuit pattern to be formed and other patterns already formed on the semiconductor wafer. The offset causes a reduction in the yield of semiconductor integrated circuit obtained from the reticle mask. Even if the offset amount may be determined on the semiconductor wafer, there is substantially no way of determining whether it is attributable to the mask itself or the aligner (exposure unit) using the mask.